If GaAs is to have an impact on the digital integrated circuit market, it must be able to incorporate adequate amounts of high-speed memory on chip. High speed GaAs microprocessors developed to date have integrated only small amounts of memory on chip. Future designs will require large sub-2 ns on-chip caches.
To prevent destructive readout, a conventional memory cell, as illustrated in FIG. 1, requires driver transistors that are three times larger than the access transistors. To achieve high access speeds, however, relatively large access transistors are necessary. Since the only function of the driver transistor is to maintain the state of the cell, the driver transistors in conventional cells are larger than minimum size, while the access transistors are smaller than desired.
The article by Fiedler et al entitled "A GaAs 256.times.4 Static Self-Timed Random Access Memory" IEEE GaAs IC Symposium Tech. Digest, November, 1986, disclosed a memory cell which utilizes current mirrors for a read operation but also requires additional devices to performs a write operation.